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SI5530
P R E L I M I N A R Y D A TA S H E E T
SiPHY TM OC-192/STM-64 SONET/SDH RECEIVER
Features
Complete low power, high speed, receiver with integrated limiting amplifier, clock and data recovery (CDR), and 1:16 demultiplexer: Data Rates Supported: OC-192/ SFI-4 Compliant LVDS Low STM-64, 10GbE, 10.7 Gbps FEC Speed Interface Low Power Operation 0.6 W (typ) Loss-of-Signal and Loss-of-Lock Detection Small Footprint 99-Pin BGA Package (11 x 11 mm) Lock-to-Reference Control Integrated Limiting Amplifier Optional 3.3 V Supply Pin for LVTTL Compatible Outputs Programmable Slicing Level and Sampling Phase Single 1.8 V Supply Operation
Si5364
Bottom View
Ordering Information:
Applications
Sonet/SDH/ATM Routers Add/Drop Multiplexers Digital Cross Connects Optical Transceiver Modules Sonet/SDH Test Equipment
See page 16.
Description
The SI5530 is a fully integrated low-power receiver for high-speed serial communication systems. It combines post amplification, clock and data recovery, and a 1:16 deserialization as required in OC-192/STM-64 applications. Support for data streams up to 10.7 Gbps is also provided for applications that employ forward error correction (FEC). A fully integrated clock and data recovery unit with integrated loop filter ensures optimal jitter performance while reducing design complexity. The SI5530 represents a new standard in low power and small size for high-speed serial receivers. It operates from a single 1.8 V supply over the industrial temperature range (-40C to 85C).
Functional Block Diagram
P HAS E _ADJ S LICE _LVL LO S LO S LV L 1:16 DEMUX RX DIN 2
L im iting AM P
RX LO L
LTR RX SQ LCH RX M S BS E L 32
CDR
RX DO UT[15:0]
RE FCLK RE FRATE RE S E T
2
2
/
Reset Control V oltage Ref Bias
2
RX CLK1 RX CLK2 RX CLK2DIV RX CLK2DS BL
V RE F
RE XT
Preliminary Rev. 0.31 8/01
Copyright (c) 2001 by Silicon Laboratories
SI5530-DS031
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si 5530
2
Preliminary Rev. 0.31
SI5530 TA B L E O F CONT E N TS
Section Page
4 8 8 8 8 8 8 9 9 9 9 9 9 9 10 10 11 13 16 17 18
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss-of-Signal Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slicing Level Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Phase Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lock-to-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Input to Parallel Output Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SI5530 Pinout: 99-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI5530 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.31
3
Si 5530
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature LVTTL Output Supply Voltage SI5530 Supply Voltage Symbol TA VDD33 VDD Test Condition Min* -40 1.71 1.71 Typ 25 -- 1.8 Max* 85 3.47 1.89 Unit C V V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated.
V SIGNAL + Differential VICM, VOCM I/Os SIGNAL - VIS Single Ended Voltage
(SIGNAL +) - (SIGNAL -) Differential Voltage Swing VID,VOD (VID = 2VIS) Differential Peak-to-Peak Voltage t
Figure 1. Differential Voltage Measurement (RXDIN, RXDOUT, RXCLK1, RXCLK2)
RXDOUT tCH RXCLK1 tcq1 tcq2 tCP
Figure 2. Data to Clock Delay
All Differential IOs tF tR
80% 20%
Figure 3. Rise/Fall Time Measurement
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Preliminary Rev. 0.31
SI5530
Table 2. DC Characteristics
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current Power Dissipation Voltage Reference (VREF) Common Mode Input Voltage (RXDIN) Differential Input Voltage Swing (RXDIN) LVPECL Input Voltage HIGH (REFCLK) LVPECL Input Voltage LOW (REFCLK) LVPECL Input Voltage Swing, Differential pk-pk (REFCLK) LVPECL Internally Generated Input Bias (REFCLK) LVDS Output High Voltage (RXDOUT, RXCLK1, RXCLK2) LVDS Output Low Voltage (RXDOUT, RXCLK1, RXCLK2) LVDS Output Voltage, Differential pk-pk (RXDOUT, RXCLK1, RXCLK2) LVDS Common Mode Voltage (RXDOUT, RXCLK1, RXCLK2) Output Short to GND (RXDOUT, RXCLK1, RXCLK2) Output Short to VDD (RXDOUT, RXCLK1, RXCLK2) LVTTL Input Voltage Low (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET) LVTTL Input Voltage High (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET) LVTTL Input Low Current (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET) LVTTL Input High Current (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET)
IDD PD VREF VICM VID VIH VIL VID VIB VOH1 VOL1 VOSE 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line, Figure 1 Figure 1 See Figure 1 VREF driving 10 k load
-- -- 1.21 TBD 20 1.975 1.32 250 1.65 TBD 0.925 500
278 0.5 1.25 0.1 -- 2.3 1.6 -- 1.95 -- -- --
TBD TBD 1.29 TBD 1.0 2.59 1.99 2400 2.3 1.475 TBD 800
mA W V V mV (pk-pk) V V mV (pk-pk) V mV V mV (pk-pk) V mA
A
VCM ISC(-) ISC(+) VIL2 VDD33 = 3.3 V VDD33 = 1.8 V VIH2 VDD33 = 3.3 V VDD33 = 1.8 V IIL
1.125 -- TBD -- -- 2.0 1.7 --
-- 25 -100 -- -- -- -- --
1.275 TBD -- 0.8 0.7 -- -- 10
V
V
A
IIH
--
--
10
A
Preliminary Rev. 0.31
5
Si 5530
Table 2. DC Characteristics (Continued)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
LVTTL Input Impedance (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET) LVTTL Output Voltage Low (LOS, RXLOL) LVTTL Output Voltage High (LOS, RXLOL)
RIN
10
--
--
k
VOL2
VDD33 = 1.8 V VDD33 = 3.3 V
-- -- 1.4 2.4
-- -- -- --
0.4 0.4 -- --
V
VOH2
VDD33 = 1.8 V VDD33 = 3.3 V
V
Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Clock Frequency (RXCLK1) Duty Cycle (RXCLK1, RXCLK2) Output Rise and Fall Times (RXCLK1, RXCLK2,RXDOUT) Data Invalid Prior to RXCLK1 Data Invalid After RXCLK1 Input Return Loss (RXIN) Slicing Adjust Dynamic Range Slicing Level Offset (referred to RXDIN)
1
fclkout
See Figure 2 tch/tcp, Figure 2
-- 45 -- -- -- 18.7 TBD -20 -500 -5 -45
o
622.08 -- 50 -- -- -- -- -- -- -- -- -- -- --
667 55 -- 200 200 -- -- 20 500 5 45
o
MHz % ps ps ps dB dB mV
V
tR,tF tcq1 tcq2
Figure 3 Figure 2 Figure 2 400 kHz-10.0 GHz 10.0 GHz-16.0 GHz SLICELVL = 200-800 mV SLICELVL = 200-800 mV VSLICE
Slicing Level Accuracy Sampling Phase Adjustment
2
% mV pk-pk
V
PHASEADJ = 200-800 mV LOSLVL = 200-800 mV LOSLVL = 200-800 mV VLOS
LOS Threshold Dynamic Range LOS Threshold Offset3 (referred to RXDIN) LOS Threshold Accuracy
10 -500 -5
50 500 5
%
Note: 1. Slice level (referred to RXDIN) is calculated as follows: VSLICE = (SLICE_LVL - 0.4 VREF)/15. 2. Sample Phase Offset is calculated as follows: PHASE OFFSET = 45 (PHASEADJ - 0.4 VREF)/0.3 3. LOS Threshold voltage (referred to RXDIN) is calculated as follows: VLOS = 30mV + (LOS_LVL - 0.4 VREF)/15.
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Preliminary Rev. 0.31
SI5530
Table 4. AC Characteristics (PLL Characteristics)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
JTOL(PP)
f = 2.4 kHz f = 24 kHz f = 400 kHz f = 4 MHz
15 1.5 1.5 0.15 -- -- -- 40 -100 TBD
30 3.0 3.0 0.3 -- 622 155 50 -- 600
-- -- -- -- 20 667 167 60 100 1000
UIPP UIPP UIPP UIPP
s
Acquisition Time
TAQ REFRATE = 1 REFRATE = 0
Input Reference Clock Frequency RCFREQ Reference Clock Duty Cycle Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock) RCDUTY RCTOL LOL
MHz MHz % ppm ppm
LOCK
TBD
300
TBD
ppm
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Table 5. Absolute Maximum Ratings
Parameter Symbol Value Unit
DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Package Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k)
VDD VDD33 VDIF TJCT TSTG
-0.5 to TBD -0.5 to 3.6 -0.3 to (VDD+ 0.3) 50 -55 to 150 -55 to 150 275 TBD
V V V mA
C C C
V
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 6. Thermal Characteristics
Parameter Symbol JA Test Condition Value Unit C/W
Thermal Resistance Junction to Ambient
Still Air
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Preliminary Rev. 0.31
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SI5530
Functional Description
The SI5530 is a high performance, low power, fully integrated receiver for SONET/SDH applications operating at OC-192/STM-64 data rates. It saves board space by integrating a limiting amplifier, clock and data recovery unit, and a demultiplexer into a small 99-pin BGA package. Further space savings are realized because no external loop filter components are required to support CDR operation. The SI5530 also provides a low-speed LVDS interface that is compliant to the Optical Interface Forums SFI-4 standard. To support long haul transmission applications, operation at data rates up to 10.7 Gbps is supported to accommodate forward error correction (FEC). In addition, programmable data slicing and sampling phase adjustment are provided to support bit-error-rate (BER) optimization. the VREF pin. The LOS detection circuitry is disabled by tieing the LOSLVL input to the supply (VDD). This forces the LOS output high.
Slicing Level Adjustment
To support applications that require BER optimization, the limiting amplifier provides circuitry that supports adjustment of the 0/1 decision threshold (slicing level) over a range of 20 mV when referred to the RXDIN input. The slicing level is set by applying a voltage between 0.20 V and 0.80 V to the SLICELVL input. The voltage present on SLICELVL sets the slicing level as follows:
( V SLICE - 0.4xVREF ) V LEVEL = ---------------------------------------------------------15
Limiting Amplifier
The SI5530 incorporates a high sensitivity limiting amplifier with sufficient gain to directly accept the output of transimpedance amplifiers. High sensitivity is achieved by using a digital calibration algorithm to cancel out amplifier offsets. This algorithm achieves superior offset cancellation by using statistical averaging to remove noise that can degrade more traditional calibration routines. The limiting amplifier provides sufficient gain to fully saturate with input signals that are less than 20 mV peak-to-peak differential. In addition, input signals that exceed 1 V peak-to-peak differential will not cause any performance degradation.
VLEVEL is the slicing level referred to the RXDIN input, VSLICE is the voltage applied to the SLICE_LVL pin, and VREF is reference voltage output on the VREF pin. The slicing level adjustment may be disabled by tieing the SLCLVL input to the supply (VDD). When slicing is disabled, the slicing offset is set to 0.0 V relative to internally biased input common mode voltage for RXDIN.
Clock and Data Recovery (CDR)
The SI5530 uses an integrated CDR to recover clock and data from a non-return to zero (NRZ) signal input on RXDIN. The recovered data clock is used to regenerate the incoming data by sampling the output of the limiting amplifier at the center of the NRZ bit period. The recovered clock and data is then deserialized by a 1:16 demultiplexer and output via a LVDS compatible low speed interface (RXDOUT[15:0], RXCLK1, and RXCLK2).
Loss-of-Signal Detection
The limiting amplifier includes circuitry that generates a loss-of-signal (LOS) alarm when the input signal amplitude on RXDIN falls below an externally controlled threshold. The SI5530 can be configured to drive the LOS output low when the differential input amplitude drops below a threshold set between ~10 mV and 50 mV pk-pk differential. Approximately 3 dB of hysteresis prevents unnecessary switching on LOS. The LOS threshold is set by applying a voltage between 0.20 V and 0.80 V to the LOSLVL input. The voltage present on LOSLVL maps to an input signal threshold as follows:
( V LOSLVL - 0.4xVREF ) V LOS = -------------------------------------------------------------- + 30 mV 15
Sample Phase Adjustment
In applications where it is not desirable to recover data by sampling in the center of the data eye, the SI5530 supports adjustment of the CDR sampling phase across the NRZ data period. When sample phase adjustment is enabled, the sampling instant used for data recovery can be moved over a range of 45 relative to the center of the incoming NRZ bit period. Adjustment of the sampling phase is desirable when data eye distortions are introduced by the transmission medium. The sample phase is set by applying a voltage between 0.20 V and 0.80 V to the PHASEADJ input. The voltage present on PHASEADJ maps to sample phase offset as follows:
VLOS is the differential pk-pk LOS threshold referred to the RXDIN input, VLOSLVL is the voltage applied to the LOSLVL pin, and VREF is reference voltage output on
Preliminary Rev. 0.31
8
Si 5530
45x ( V PH ASE - 0.4xVREF ) PhaseOffset = ------------------------------------------------------------------------0.30
Phase Offset is the sampling offset in degrees from the center of the data eye, VPHASE is the voltage applied to the PHASEADJ pin, and VREF is reference voltage output on the VREF pin. A positive phase offset will adjust the sampling point to lead the default sampling point at the center of the data eye, and a negative phase offset will adjust the sampling point to lag the default sampling point. Data recovery using a sampling phase offset is disabled by tieing the PHASEADJ input to the supply (VDD). This forces a default phase offset of 0 to be used for data recovery.
be scaled accordingly. For example, to support 10.66 Gbps operation the REFCLK frequencies would be approximately 166 MHz or 666 MHz. The REFRATE input pin is used to configure the device for operation with one of the two supported reference clock submultiples of the data rate.
Deserialization
The SI5530 uses a 1:16 demultiplexer to deserialize the high-speed input. The deserialized data is output on a 16-bit parallel data bus RXDOUT[15:0] synchronous with the rising edge of RXCLK1. This clock output is derived by dividing down the recovered clock by a factor of 16.
Lock Detect
The SI5530 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. This circuit compares the frequency of a divided down version of the recovered clock with the frequency of the supplied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 4 on page 7, the PLL is declared out of lock, and the loss-oflock (RXLOL) pin is asserted. In this state, the PLL will try to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (RXCLK1 and RXCLK2) will drift over a 1% range relative to the supplied reference clock. The RXLOL output will remain asserted until the recovered clock frequency is within the REFCLK frequency by the amount specified in Table 4 on page 7.
Serial Input to Parallel Output Relationship
The SI5530 provides the capability to select the order in which the received serial data is mapped to the parallel output bus RXDOUT[15:0]. The mapping of the receive bits to the output data word is controlled by the RXMSBSEL input. If RXMSBSEL is tied low, the first bit received is output on RXDOUT0 and the following bits are output in order on RXDOUT1 through RXDOUT15. If RXMSBSEL is tied high, the first bit received is output on RXDOUT15, and the following bits are output in order on RXDOUT14 through RXDOUT0.
Auxiliary Clock Output
To support the widest range of system timing configurations, a second clock output is provided on RXCLK2. This output can be configured to provide a clock that is a 1/16th or 1/64th submultiple of the high speed recovered clock. The divide factor used to generate RXCLK2 is controlled via the RXCLKDIV2 input as described in "Pin Descriptions: SI5530" on page 13. In applications which do not use RXCLK2, this output can be powered down by forcing the RSCLK2DSBL input high.
Lock-to-Reference
In applications where it is desirable to maintain a stable output clock during an alarm condition like loss-ofsignal, the lock-to-reference input (LTR) can be used to force a stable output clock. When LTR is asserted, the CDR is prevented from acquiring the data signal and the CDR will lock the RXCLKOUT1 and RXCLKOUT2 outputs to the provided REFCLK. In typical applications, the LOS output would be tied to the LTR input to force a stable output clock.
Data Squelch
During some system error conditions, such as LOS, it may be desirable to force the receive data output to zero in order to avoid propagation of erroneous data into the downstream electronics. In these applications, the SI5530 provides a data squelching control input, RXSQLCH. When this input is active low, the data on RXDOUT will be forced to 0.
Reference Clock
The CDR within the SI5530 uses a reference clock to center the PLL frequency so that it is close enough to the data frequency to achieve lock. The device is designed to operate with reference clock sources that are either 1/16th or 1/64th the input data rate. The SI5530 will operate with data streams between 9.9 Gbps and 10.7 Gbps and the reference clock should
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Preliminary Rev. 0.31
SI5530
Bias Generation Circuitry
The SI5530 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption versus traditional implementations that use an internal resistor. The bias generation circuitry requires a 3.09 k (1%) resistor connected between REXT and GND.
Voltage Reference Output
The SI5530 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjust. One possible implementation would use a resistor divider to set the control voltage for LOSLVL, SLICELVL, or PHASEADJ. A second alternative would use a DAC to set the control voltage. Using this approach, VREF would be used to establish the range of a DAC output. The reference voltage is nominally 1.25 V.
Preliminary Rev. 0.31
10
SI5530
SI5530 Pinout: 99 BGA
10
9
8
7
6
5
4
3
2
1
RXDOUT[4]+
RXDOUT[2]-
RXDOUT[2]+
RXDOUT[0]-
RXDOUT[0]+
RXCLK[1]-
RXCLK[1]+
RXCLK2 DSBL
REXT
A
RXDOUT[4]-
RXDOUT[3]-
RXDOUT[3]+
RXDOUT[1]-
RXDOUT[1]+
RXCLK[2]-
RXCLK[2]+
NC
VREF
SLICELVL
B
RXDOUT[6]+
RXDOUT[5]+
GND
GND
GND
GND
GND
RSVD_ GND
LOSLVL
PHASEADJ
C
RXDOUT[6]-
RXDOUT[5]-
GND
VDD
VDD
VDD
VDD
RXSQLCH
GND
GND
D
RXDOUT[8]+
RXDOUT[7]+
GND
VDD
VDD
VDD
VDD
RSVD_ GND
GND
RXDIN+
E
RXDOUT[8]-
RXDOUT[7]-
GND
VDD
VDD
VDD
VDD
RSVD_ GND
GND
RXDIN-
F
RXDOUT[10]+ RXDOUT[9]+
GND
VDD
VDD
VDD
VDD
RSVD_ VDD33
GND
GND
G
RXDOUT[10]-
RXDOUT[9]-
GND
GND
GND
GND
GND
VDD33
RSVD_ GND
LTR
H
RXDOUT[12]+ RXDOUT[11]+ RXDOUT[11]- RXDOUT[13]+ RXDOUT[13]- RXDOUT[15]+ RXDOUT[15]-
REFRATE
RSVD_ VDD33
RXLOL
J
RXDOUT[12]- RXDOUT[14]+ RXDOUT[14]-
REFCLK+
REFCLK-
RSVD_ GND
RXMSBSEL
RXCLK2DIV
RESET
LOS
K
Bottom View
Figure 4. SI5530 Pin Configuration (Bottom View)
Preliminary Rev. 0.31
11
Si 5530
1 2 3 4 5 6 7 8 9 10
A
REXT
RXCLK2 DSBL
RXCLK[1]+
RXCLK[1]-
RXDOUT[0]+
RXDOUT[0]-
RXDOUT[2]+
RXDOUT[2]-
RXDOUT[4]+
B
SLICELVL
VREF
NC
RXCLK[2]+
RXCLK[2]-
RXDOUT[1]+
RXDOUT[1]-
RXDOUT[3]+
RXDOUT[3]-
RXDOUT[4]-
C
PHASEADJ
LOSLVL
RSVD_ GND
GND
GND
GND
GND
GND
RXDOUT[5]+
RXDOUT[6]+
D
GND
GND
RXSQLCH
VDD
VDD
VDD
VDD
GND
RXDOUT[5]-
RXDOUT[6]-
E
RXDIN+
GND
RSVD_ GND
VDD
VDD
VDD
VDD
GND
RXDOUT[7]+
RXDOUT[8]+
F
RXDIN-
GND
RSVD_ GND
VDD
VDD
VDD
VDD
GND
RXDOUT[7]-
RXDOUT[8]-
G
GND
GND
RSVD_ VDD33
VDD
VDD
VDD
VDD
GND
RXDOUT[9]+ RXDOUT[10]+
H
LTR
RSVD_ GND
VDD33
GND
GND
GND
GND
GND
RXDOUT[9]-
RXDOUT[10]-
J
RXLOL
RSVD_ VDD33
REFRATE
RXDOUT[15]- RXDOUT[15]+ RXDOUT[13]- RXDOUT[13]+ RXDOUT[11]- RXDOUT[11]+ RXDOUT[12]+
K
LOS
RESET
RXCLK2DIV
RXMSBSEL
RSVD_ GND
REFCLK-
REFCLK+
RXDOUT[14]- RXDOUT[14]+ RXDOUT[12]-
Top View
Figure 5. SI5530 Pin Configuration (Transparent Top View)
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Preliminary Rev. 0.31
SI5530
Pin Descriptions: SI5530
Pin Number(s)
Name
I/O
Signal Level GND.
Description
C4-8, D8, D1- 2, E8, E2, F8, F2, G8, G1-2, H4-8 K1
GND
GND
LOS
O
LVTTL
Loss-of-Signal. This output is driven low when the peak-to-peak signal amplitude is below threshold set via LOSLVL. LOS Threshold Level. Applying an analog voltage to this pin allows adjustment of the Threshold used to declare LOS. Tieing this input high disables LOS detection and forces the LOS output high. Lock-to-Reference. This input forces a stable output clock by locking RXCLK1 and RXCLK2 to the provided reference. Driving LTR low activates this feature. No Connect. Reserved for device testing leave electrically unconnected.
C2
LOSLVL
I
--
H1
LTR
I
LVTTL
B3
NC
C1
PHASEADJ
I
--
Sampling Phase Adjust. Applying an analog voltage to this pin allows adjustment of the sampling phase across the data eye. Tieing this input high nominally centers the sampling phase. Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock and data recovery. The device will operate with reference frequencies that are 1/16th or 1/64th the input data rate (nominally 155 MHz or 622 MHz). Reference Clock Select. This input configures the SI5530 to operate with one of two reference clock frequencies. If REFSEL is held high, the device requires a reference clock that is 1/16 the input data rate. If REFSEL is low, a reference clock at 1/64 the input data rate is required. Device Reset. Forcing this input low for a at least 1s will cause a device reset. For normal operation, this pin should be held high.
K6-7
REFCLK-, REFCLK+
I
LVPECL
J3
REFRATE
I
LVTTL
K2
RESET
I
LVTTL
Preliminary Rev. 0.31
13
Si 5530
Pin Number(s) Name I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 3.09 k (1%) resistor. Reserved Tie to Ground. Must tie directly to GND for proper operation. Reserved Tie to VDD33. Must tie directly to VDD33 for proper operation.
A2
REXT
C3, E3, F3, H2, K5 G3, J2 A4-5
RSVD_GND RSVD_VDD33 RXCLK1+, RXCLK1- O LVDS
Differential Clock Output 1. The clock recovered from the signal present on RXDIN is divided down by 16 and output on CLKOUT. In the absence of data, a stable clock on RXCLK1 can be maintained by asserting LTR. Differential Clock Output 2. An auxiliary output clock is provided on this pin that may be a divided down version of the high speed clock recovered from the signal present on RXDIN. The divide factor used in generating RXCLK2 is set via RXCLK2DIV. Clock Divider Select. This input selects the divide factor used to generate the RXCLK2 output. When this input is driven low, RXCLK2 is 1/16th the recovered high-speed clock. When driven high, RXCLK2 is 1/64th the recovered high speed clock rate. RXCLK2 Disable. Driving this input high will disable the RXCLK2 output. This would be used to save power in applications that do not require an auxiliary clock. Differential Data Input. Clock and data are recovered from the high speed data signal present on these pins. Differential Parallel Data Output. The data recovered from the signal present on RXDIN is demultiplexed and output as a 16-bit parallel word via RXDOUT[15:0]. These outputs are updated on the rising edge of RXCLK1. Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 4.
B4-5
RXCLK2+, RXCLK2-
O
LVDS
K3
RXCLK2DIV
I
LVTTL
A3
RXCLK2DSBL
I
LVTTL
E1, F1
RXDIN+, RXDIN-
I
High Speed Differential LVDS
A6-10, B6-10, RXDOUT[15:0]-, C9-10, D9-10, RXDOUT[15:0]+ E9-10, F9-10, G9-10, H9-10, J4-10, K8-10 J1 RXLOL
O
O
LVTTL
14
Preliminary Rev. 0.31
SI5530
Pin Number(s) Name I/O Signal Level Description Data Bus Receive Order. This determines the order of the received data bits on the output bus. For RXMSBSEL = 0, the first data bit received is output on RXDOUT[0] and following data bits are output on RDOUT[1] through RXDOUT[15]. For RXMSBSEL = 1, the first data bit is output on RXDOUT[15] and following data bits are output on RXDOUT[14] through RXDOUT[0]. Data Squelch. When this input is low, the data on RXDOUT is forced to 0. Set RXSQLCH high for normal operation. Slicing Level Adjustment. Applying an analog voltage to this pin allows adjustment of the slicing level applied to the input data eye. Tieing this input high nominally sets the slicing offset to 0. Supply Voltage. Nominally 1.8 V.
K4
RXMSBSEL
I
LVTTL
D3
RXSQLCH
I
LVTTL
B1
SLICELVL
I
--
D4-7, E4-7, F4-7, G4-7, H3
VDD VDD33
VDD VDD33
1.8 V
1.8 V or 3.3 V Digital Output Supply. Must be tied to either 1.8 V or 3.3 V. When tied to 3.3 V, LVTTL compatible output voltage swings on RXLOL and LOS are supported. Voltage Ref
Voltage Reference. The Si5600 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjustment. The equivalent resistance between this pin and GND should not be less than 10 k. The reference voltage is nominally 1.25 V.
B2
VREF
O
Preliminary Rev. 0.31
15
Si 5530
Ordering Guide
Table 7. Ordering Guide Part Number Package Temperature
SI5530-BC
99 BGA
-40C to 85C
16
Preliminary Rev. 0.31
SI5530
Package Outline
Figure 6 illustrates the package details for the SI5530. Table 8 lists the values for the dimensions shown in the illustration.
A1 Ball Pad Corner A D A1
10 9 8 7 6 5 4 3 2 1
A1 Ball Pad Corner
e
A B C D
E b 1.00 Ref
E F G H J K
1.00 Ref A2 Seating Plane
e
Top View
Side View
Bottom View
Figure 6. 99-Ball Grid Array (BGA)
Table 8. Package Diagram Dimensions
Symbol Min 1.30 0.31 0.65 -- -- -- -- Millimeters Nom 1.40 0.36 0.70 0.46 11.00 11.00 1.00 Max 1.50 0.41 0.75 -- -- -- --
A A1 A2 b D E e
Preliminary Rev. 0.31
17
Si 5530
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and SiPHY are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
18
Preliminary Rev. 0.31

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